modelsim 시뮬레이션과 initial

당연히(?) initial은 있어야 하는데

모듈내에서 사용하는 reg 변수들에 대해서도 처리가 되어 있지 않으면

값이 X가 나오면서 garbage 값이라 처리를 못하는 것으로 보인다.

예전에 구한 소스인데, 시뮬레이션 안되던거 혹시나 해서

모듈내에 사용되는 reg 변수를 0으로 초기화 해주니 시뮬레이션이 잘 진행된다.

module vga640x480( input clk, input rst, output [7:0] LED, output reg hsync, output reg vsync, output [3:0] r, output [3:0] g, output [3:0] b ); reg clk25; reg [9:0] horizontal_counter; reg [9:0] vertical_counter; reg [9:0] X; reg [9:0] Y; wire [7:0] red; wire [7:0] green; wire [7:0] blue; initial begin horizontal_counter = 0; vertical_counter = 0; end assign r[3:0] = ((horizontal_counter >= 144)  && (horizontal_counter < 784)  && (vertical_counter >=39) && (vertical_counter < 519)) ? red : 4'b000;  assign g[3:0] = ((horizontal_counter >= 144)  && (horizontal_counter < 784)  && (vertical_counter >=39) && (vertical_counter < 519)) ? green : 4'b000;  assign b[3:0] = ((horizontal_counter >= 144)  && (horizontal_counter < 784)  && (vertical_counter >=39) && (vertical_counter < 519)) ? blue : 4'b000;  assign red =   ((horizontal_counter >= 144)&&(horizontal_counter < 344) ) ? 4'b1111 : 4'b0000; assign green = ((horizontal_counter >= 344)&&(horizontal_counter < 544) ) ? 4'b1111 : 4'b0000; assign blue =  ((horizontal_counter >= 544)&&(horizontal_counter < 784) ) ? 4'b1111 : 4'b0000; always @(posedge clk) begin if (clk25 == 0) begin    clk25 <= 1; end    else begin clk25 <= 0;    end end always @(posedge clk25) begin if ((horizontal_counter > 0) && (horizontal_counter < 97))// -- 96+1 begin hsync <= 0; end else begin hsync <= 1; end  if ((vertical_counter > 0 ) && (vertical_counter < 3 )) //-- 2+1 begin vsync <= 0; end else begin vsync <= 1; end horizontal_counter <= horizontal_counter+1;      if (horizontal_counter == 800)  begin vertical_counter <= vertical_counter+1; horizontal_counter <= 0; end      if (vertical_counter == 521) begin vertical_counter <= 0; end end endmodule