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13:01:21 **** Incremental Build of configuration Nios II for project hello_world_0_bsp ****

make all 

Makefile not up to date.

../../unsaved.sopcinfo has been modified since the BSP was generated.

Generate the BSP to update the Makefile, and then build again.

To generate from Eclipse:

 1. Right-click the BSP project.

 2. In the Nios II Menu, click Generate BSP.

To generate from the command line:

 nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>

make: *** [public.mk] Error 1

13:01:22 Build Finished (took 946ms)

• A Dhrystone 2.1 performance rating of 0.252 DMIPS/MHz yields an unmatched 26.85 times speed up over the original 80C51 chip operating at the same frequency.
• Maximum CPU frequency exceeds 500 MHz for a class-leading effective increase of more than 1,000 times over 80C51 chips (40nm G process) 

EPCS Controller-Based Boot Copier

EPCS controller-based boot copier supports EPCS memory only. Boot copier is stored in the ROM within

the EPCS flash controller. The boot copier is included during Qsys and Quartus Prime project compila‐

tion time.

The next stage boot image is located in the EPCS memory flash. The EPCS controller-based boot copier is

automatically appended into the SREC image (*.flash) file during the elf2flash utility execution in the

Nios II Flash Programming flow method.

EPCS Controller-Based Boot Copier

EPCS controller-based boot copier supports EPCS memory only. Boot copier is stored in the ROM within

the EPCS flash controller. The boot copier is included during Qsys and Quartus Prime project compila‐

tion time.

The next stage boot image is located in the EPCS memory flash. The EPCS controller-based boot copier is

automatically appended into the SREC image (*.flash) file during the elf2flash utility execution in the

Nios II Flash Programming flow method. 

My application contains:

1. Clock Source

2. Nios II Processor

3. System ID

4. JTAG UART

5. EPCS Serial Flash Controller

6. PIO

7. SDRAM Controller

Make sure the Nios II’s Reset Vector is pointing at EPCS/EPCQ Controller. 

Nios II Gen2 Processor Feature Enhancements

The Nios II Gen2 processor family consists of /e and /f cores. It offers improvements over the Nios II Classic processor cores:

• Optional full 32-bit address space 

• Optional user-defined Peripheral address region for data cache bypass 

• Improved Qsys interface

The Nios II Gen2 /e core is completely backwards compatible with the Nios II Classic /s core. The Nios II Classic /s core has no direct equivalent in the Nios II Gen 2 family, however the Nios II Gen2 /f processor (as it has a more flexible configuration capability) can be configured to have the same feature set as the Nios II Classic /s core.

The Nios II Gen2 /f core offers the following feature enhancements over the Nios II Classic /f core: 

• Optional full ECC support, including data cache and TCMs (Tightly-coupled Memories) 

• Optional static branch prediction 

• Higher performance multiplier

• Improved and more deterministic divider 

• 64-bit multiply supported on all devices 

• Improved low-cost shifter implementation up to 4 bits/cycle 

• Instruction cache is now optional even when JTAG debug is present 

• New system interface for system trace 

C:\intelFPGA_lite\17.1\nios2eds\bin

C:\intelFPGA_lite\17.1\nios2eds\bin\gnu\H-x86_64-mingw32\bin 

D:\>C:\intelFPGA_lite\17.1\nios2eds\bin\elf2flash.exe --input=hello_world_0.elf --output=swimage.flash --epcs

D:\>dir

2018-01-27  오후 01:19               946 hello_world.c

2018-01-27  오후 01:20           319,239 hello_world_0.elf

2018-01-27  오후 01:20            86,021 hello_world_0.map

2018-01-29  오후 01:53            11,824 swimage.flash

D:\>C:\intelFPGA_lite\17.1\nios2eds\bin\gnu\H-x86_64-mingw32\bin\nios2-elf-objcopy.exe -I srec -O ihex swimage.flash  swimage.hex

D:\>dir

2018-01-27  오후 01:19               946 hello_world.c

2018-01-27  오후 01:20           319,239 hello_world_0.elf

2018-01-27  오후 01:20            86,021 hello_world_0.map

2018-01-29  오후 01:53            11,824 swimage.flash

2018-01-29  오후 01:57            13,272 swimage.hex 

S00600002D454C3B

S325000000007C0F00000000010074004000140840083A6800080000000000000000000000008C

S3250000002000000000000000007400C0061400E0DE74008006148CA4D67400800014498510B4

S325000000407400C000144DC5182603C010150000100401801036FDFF10C0251000C03310003B

:100000007C0F00000000010074004000140840084C

:100010003A68000800000000000000000000000036

:1000200000000000000000007400C0061400E0DEC4

:1000300074008006148CA4D67400800014498510C6

sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose

elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

nios2-elf-objcopy -I srec -O ihex hwimage.flash  hwimage.hex

nios2-elf-objcopy -I srec -O ihex swimage.flash  swimage.hex 

The method used to create a .jic file with a Nios® II hardware and software image is as follows.

1. Create a flash file from a .sof file: sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose

2. Create a flash file from a ,elf file: elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

3. Convert the .flash image into a.hex file: nios2-elf-objcopy --input-target srec --output-target ihex mysw.flash mysw.hex

4. In the Quartus® II software, open File > Convert Programming Files > Set the programming file as JTAG Indirect Configuration File (.jic).

6. Select the correct size EPCS device in the Configuration pull-down

7. Name your output .jic file

8. Click Flash Loader below, and select Add Device on the right hand side

9. Select your FPGA device from the list

10. Click SOF Data, and select Add File, and select your .sof file

11. Click Add Hex data, select Relative addressing, and select your .hex file created above

12. Now push generate. You should verify that the generated .map file has Page_0 at a start address of 0x0, and the hex file at a start address 1 after the end address of Page_0

13. Now in the Quartus II Programmer, select Add File and select your .jic file. Check the Program box next to the .jic file, and push Start 

The method used to create a .jic file with a Nios® II hardware and software image is as follows.

1.      Create a flash file for the hardware and software image
sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose
elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose

Note: When creating the software flash image, there is no need to add a boot srec (this is located in the EPCS Controller), the --after option ensures the software image starts immediately after the hardware image.

2.      Convert the flash images into Hex files

nios2-elf-objcopy -I srec -O ihex hwimage.flash  hwimage.hex
nios2-elf-objcopy -I srec -O ihex swimage.flash  swimage.hex

3.      When creating your jic file using Quartus® II Convert Programming File tool, add the Flash Loader and both hex files with absolute addressing option selected.

Note: You do not need to add the .sof file to the jic image.  This is because you created a hardware hex image.  Using the hardware hex image ensures the software hex image is at the proper offset in the EPCS.